IIT Bombay's Prof Souvik Mahapatra Honoured With Named Model For Enhancing Semiconductor Reliability

In a groundbreaking recognition, the semiconductor industry has introduced the “Mahapatra reliability model” named after Professor Souvik Mahapatra of Indian Institute of Technology, Bombay. He was honoured with named model for his work on chip reliability, which has been helping semiconductor manufacturers to make reliable electronic chips. 

Prof. Souvik Mahapatra of the Department of Electrical Engineering, has been spearheading the efforts to characterize, understand, model and control transistor reliability for over two decades. He collaborates closely with several leading industries in the semiconductor chip ecosystem, including IBM, Intel, Micron, Applied Materials and Synopsys to name a few. As a result of his effort, the semiconductor industry, now has a methodology for characterizing and optimizing reliability across various advanced CMOS logic and memory technologies. 

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“The degradation of transistor performance at normal operating conditions of a chip becomes appreciable only at a very long time close to the end of product life. Since reliability must be estimated during technology development, short time accelerated stress tests are done to speed up transistor degradation, and theoretical projection methods are used to estimate its severity at the end-of-life under normal operating conditions”, said Prof. Mahapatra. 

He added, “Error in the theoretical model can lead to either underestimation or overestimation of degradation during the technology development phase with significant consequences; either the release of a defective product or an unnecessary increase in the expense and time due to over optimization”.

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As a result of his collaboration with Synopsys, a reliability model has been developed and incorporated in Sentaurus Device TCAD (named as “Mahapatra Reliability Model”), which is being used by several industries in the logic and memory areas of the semiconductor ecosystem. It also has acknowledged Prof. Mahapatra’s achievement with an award, which was given at their event during the International Electron Devices Meeting (IEDM) in San Francisco in December 2024.

Dr. Chandra Mouli, Vice President of Micron lauded Malhotra for his exceptional understanding of transistor reliability challenges and called his collaboration as a “fruitful and indispensable.” IBM’s Dr. Mukesh Khare praised his advancements in logic technology scaling, while Synopsys has integrated his model into their TCAD software, acknowledging his achievements with an award at the International Electron Devices Meeting (IEDM) 2024.